+FET Super Junction Technology                    

At D3, we believe power, precision and efficiency are inextricably linked. Our +FET technology is borne from the desire to fuse the power and efficiency of Super Junction architectures with the precision of mixed-signal capabilities. 

We founded D3 on the premise to change the DNA of power conversion and motor control.  We are driving to the next stage of evolution in power technology building blocks.  Our technology will equip the designer with tools needed to increase power densities to new levels using standard silicon power technology.

 

Step 1: Re-think Power MOSFETs -- Efficiency at every turn

To start our journey, we had to build a world-class Super Junction MOSFET.  We bench-marked the competition and set out to achieve best-in-class MOSFET power density.  Deploying mixed-signal design technology gave us the best possible outcome before moving a single wafer.

In our measurements of critical parameters, +FET outperforms the competition and shows signs of excellent switching behavior.  Low Rds-On coupled with excellent switching behavior yields higher efficiency.


 

Step 2: Robust and reliable

The technology must be robust.  We targeted the 650V node as our customers demand the highest possible level of performance and reliability. 
By building a 650V FET with robust EAS performance and diode ruggedness, +FET can now improve power densities of applications traditionally served by IGBTs such as inverters and motor drives.

 

Step 3:  Stress test the technology

Long life and reliability are intrinsic to the +FET technology.  In addition to mixed-signal design techniques, we employ mixed-signal manufacturing practices.  This is not seen in the discrete market.  By making simple changes to manufacturing, big gains can be achieved in reliability.
Sure, we used the JESD-22 testing methods for reliability testing.  However, we went further.  We ran the biased moisture tests to 4000 hours to gauge the effects of extremely long life, harsh operating conditions.  The results were outstanding.  In the extreme testing, we saw no appreciable drift in key MOSFET parameters.  This proved that our +FET technology is rock solid.

 

Step 4:  Build for the future

As part of the +FET architecture, we have encompassed the future of Super Junction technology.  In the future, we will place more control of dynamic parameters in the hands of the engineer.  +FET is only the beginning for D3 Semiconductor.

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